One or more clock signals may be distributed throughout a microprocessor to facilitate the microprocessor's operation. For example, state elements located at different points in the microprocessor die may function synchronously by operating in accordance with the clock signals.
It is known that a core Phase-Locked Loop (PLL) unit in a microprocessor can receive a reference clock signal, such as an externally generated bus clock signal, and create a core clock signal (e.g., having a frequency of N2* the frequency of the externally generated bus clock signal). The core clock signal is then provided to core state elements via a core clock distribution network (e.g., a core clock distribution tree). After being distributed, the core clock signal can be used to re-create the bus clock signal (i.e., to create a core generated bus clock signal).
Similarly, an Input Output unit (IO) PLL unit in the microprocessor can receive the externally generated bus clock signal and create an IO clock signal (e.g., having a frequency of N1* the frequency of the externally generated bus clock signal). The IO clock signal is then provided to IO state elements via an IO clock distribution network. After being distributed, the IO clock signal can be used to re-create the bus clock signal (i.e., to create an IO generated bus clock signal).
The core and IO generated bus clock signals may then be used to synchronize core and IO operations in the microprocessor. If a mis-alignment, or skew, between the core and IO generated bus clocks signals grows too large, however, information might not be properly transferred between the core and the IO. For example, differences in a core PLL unit and an IO PLL unit may result in skew between the core and IO generated bus clock signals. Similar problems can arise with other types of free-running clock systems (e.g., a clock grid). As another example, variations due to process on a core or IO clock distribution network delay could result in skew between the core and IO generated bus block signals. Such problems may become more important as clock signal frequencies increase, and the amount of skew may represent multiple core clock cycles.
It is known that skew can be reduced by adjusting a delay associated with one (or both) of the core and IO clock distribution networks. This approach, however, can require a significant default delay in the distribution networks (e.g., the network may need to have a large number of stages), which can increase clock uncertainty as well as the amount of power that is consumed by clock circuitry.